As the demand for high performance, high density integrated circuit devices increases, the ability to offer ever smaller Static Random Access Memory (SRAM) cells becomes critical. As the device feature size shrinks, the SRAM cell size becomes interconnect limited. One way to minimize the cell size is to use local interconnects (instead of metal 1 and contacts) to strap gates and diffusion areas.
In one recent prior art method for forming local interconnects, dielectric spacers are formed on each side of each gate. A portion of an dielectric spacer is removed using mask and etch steps so as to form a exposed region on the side of the gate. Self-aligned silicidation (SALICIDE) is used to form an interconnect structure that electrically connects the gate to the diffusion area.
Prior art FIG. 1A shows a diagram of a local interconnect formed according to a prior art process. Silicide region 3 extends over the top of polysilicon gate 2 and silicide region 4 extends over silicon substrate 1 such that it at least partially overlies diffusion region 5. However, the sidewall of the polysilicon gate 2 does not form a continuous layer of silicide. The poor sidewall silicidation is primarily due to metal thinning associated with sputtering shadowing and to residual surface oxide left over from prior processing steps (polysilicon reoxidation, spacer removal, etc.). Thus, the gate-to-diffusion connection relies on the silicide at the bottom corner 10 where the sidewall of polysilicon gate 2 meets silicide region 4. The resulting electrical connection is unreliable as it relies on electrical connection via the tip of silicide region 4 at bottom corner 10 and relies on conductivity through polysilicon gate 2.
In structures that use Shallow Trench Isolation (STI) for isolating diffusion areas, dielectric material is disposed in shallow trenches. When the polysilicon gate does not overlie the diffusion area, disconnection results. Prior art FIG. 1B shows a disconnection 20 that results from the placement of polysilicon gate 2 over STI dielectric 21. Disconnection problems of this type typically result from photolithography misalignment.
Another problem with prior art local interconnects is junction leakage. Junction leakage typically occurs as a result of rough silicide formation because the diffusion junction is abruptly delineated along the gate edge, creating a junction punch-through (a conductive path into the semiconductor substrate). This is in contrast to the normal situation where the source/drain extension along a spacer edge provides extra protection against silicidation induced junction leakage. FIG. 1C shows junction punch-through 30 that is a conductive path resulting from rough silicide formation during the formation of silicide region 4.
Thus, a need exists for a local interconnect and a method for forming a local interconnect that produces a local interconnect that is robust and that makes good electrical connection. Also, a local interconnect and a method for making a local interconnect is required that meets the above need and that does not have silicidation induced junction leakage. The present invention provides a solution to the above needs.